As the technology for manufacturing integrated circuits advances, more and more logic functions may be included in a single integrated circuit device. Modern integrated circuit (IC) devices include over 100,000 transistors on a single semiconductor chip, with these transistors interconnected so as to perform multiple and complex digital functions, such as, for example, those in a general-purpose microprocessor. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the design of the circuit be error free. Further, such digital circuitry is currently being integrated at increasingly higher levels with analogue circuitry resulting in Analogue Very Large Scale Integration (AVLSI). The design of these mixed (digital and analogue) circuits again must be error free. In addition, such a circuit requires that no defect be generated during its manufacture, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires various types of electrical testing after manufacture.
Development of a test program for an IC and debugging of that program can be very time consuming and costly unless designers consider test issues during the logic design phase. Due to the increased complexity of VLSI and AVLSI chips, it is generally not feasible for test engineering to independently develop and debug test programs. The responsibility now lies with logic and circuit designers to design logic and circuitry such that it is easy to test and requires a reduced set of so-called test "vectors" to thoroughly test the design.
However, as the complexity of the circuit increases, so does the cost and difficulty of verifying and electrically testing each of the devices in the circuit. From an electrical test standpoint, in order to totally verify that each of the transistors in the VLSI circuit properly function, one must theoretically be able to exercise each of the transistors not only individually (in the digital sense, determining that it is neither stuck-open or stuck-closed), but also in conjunction with the other transistors in the circuit in all possible combinations of operations. Analogue circuitry is not susceptible to such testing and instead AC and DC parametric tests are conducted to ensure the analogue devices have been properly fabricated and properly connected. This is normally accomplished by automated testing equipment (ATE) that employs test vectors to perform the desired digital or logic tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses) and expected test outputs (or signals) for every package pin for a period of time, with the purpose being to "test" a particular cell (or macro). A test vector for analogue circuitry describes the analogue stimuli and analogue outputs. For complex circuitry this may involve a large number of test vectors and accordingly a long test time. Macro and cell are used herein to mean the same thing.
In addition, specific circuit configurations in the VLSI or AVLSI circuit may have some of its devices inaccessible for all but a special combination of signals, thereby hiding a fault or defect unless a very specific pattern of signals is presented. However, the cost of performing such testing on 100% of the manufactured circuits is staggering, considering the high cost of the test equipment required to exercise each circuit in conjunction with the long time required to present each possible combination to each device. This has in the past forced integrated circuit manufacturers to test less than all of the active devices in a chip, with the attendant quality levels of the product being less than optimal. Thus, one of the major problems in integrated circuit design is the ability to adequately test the final IC design and this problem increases with increasing complexity of the integrated circuit.
The key concepts in so-called design for test (DFT) are controllability and observability. Controllability means the ability in a digital sense to set and reset every node, or in an analogue sense to apply an analogue stimulus to every node of the circuit, while observability means the ability to observe either directly or indirectly the state or value of any node in the circuit. The purpose of the various DFT techniques is to increase the ability to control and observe internal nodes from external inputs/outputs. DFT techniques may be employed for logic verification and AC/DC parametric tests.
Designing testability into any circuit will affect the circuitry to some degree. Additional logic will probably have to be added. This additional logic will increase the amount of silicon required to implement the design. The savings from enhanced testability do not usually show up until the development time and testing costs of the circuit and its end system are analyzed.
Circuit designers have used stuck-fault modeling techniques in improving the efficiency of the testing of such digital VLSI circuits. Digital stuck-fault modeling is directed not to stuck-open or stuck-closed defects in individual transistors, but to the effect of such defective transistors (and defective interconnections) resulting in stuck-high and stuck-low outputs of the logic circuit. Minimum patterns of test vectors are then derived for the exercising of the logic circuit, such test patterns being inputs to the circuit designed to cause stuck-high and stuck-low outputs if defects are present. Such techniques have been successful in improving the digital test efficiency of VLSI circuits.
In conjunction with the digital stuck-fault modeling and associated pattern generation, cooperative circuitry may be included in the VLSI circuit specifically directed to improving its testability. One configuration of this cooperative circuitry is a scan path in the logic circuit. The scan path consists of a series of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. These latches can be loaded with a serial data stream ("scan in") and can present their contents to the nodes in the logic circuit, presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation at each of the nodes (having a scan latch) stored in its respective latch. By serially unloading the contents of the latches ("scan out"), the result of the particular test operation at the associated nodes is read out and may be analyzed for improper node operation. Repetition of this operation with a number of different data patterns effectively tests all necessary combinations of the logic circuit, but with a reduced test time and cost compared to separately testing each active component or cell and all their possible interactions. Techniques for scanning such data are discussed by E. J. McCluskey in "A Survey of Design for Testability Scan Techniques", VLSI Design (Vol. 5, No. 12, pp. 38-61, December 1984).
Also as this technology is advancing, users of integrated circuits are desiring specially designed and constructed integrated circuits, for performing functions specific for the user's application. Such integrated circuits have been called Application Specific Integrated Circuits (ASICs). For an ASIC device to be cost-competitive with general purpose microcomputers which may have a special function implemented in programmable software, and to be cost-competitive with a board design made up of smaller scale integrated circuits, the design time of the ASIC circuit must be short and the ASIC circuit must be manufacturable and testable at low cost. Currently, some ASIC devices are being designed to include both digital and analogue circuitry. Accordingly, it is useful for such circuits to be modular in design, with each of the modules performing a certain function, so that a new circuit may be constructed by combining previously-designed circuit modules. Such an approach can also be used for non-ASIC microcomputers and microprocessors. Regardless of the end product, the use of a modular approach allows the designer to use logic which has previously been verified, and already been proven as manufacturable. However, if logic modules which utilize a particular scan path in their original placement in an integrated circuit are placed into a new circuit application, new test patterns will generally be required for the new device, thereby lengthening the design/manufacture cycle time.
As described in U.S. Pat. No. 4,860,290 filed Jun. 2, 1987 and assigned to Texas Instruments Incorporated, a modular approach to utilizing scan paths and other testability circuits has been used and provides thorough coverage of all possible digital faults in an efficient manner. Reduced test time and cost are thus achieved by such modularity.
Recently, MegaModule.TM. have been used in the design of application-specific integrated circuits (ASICs). (MegaModule is a trademark of Texas Instruments Incorporated.) Each of these MegaModules.TM., which for example may be SRAMs, FIFOs, register fries, RAMS, ROMS, universal asynchronous receiver-transmitters (UARTs), programmable logic arrays or other logic circuits, are usually defined as integrated circuit modules of at least 500 gates in complexity and are a complex ASIC macro function. These MegaModules.TM. may be predesigned and stored in an ASIC design library. MegaModule.TM. can then be used by the designer in the design of an ASIC by placing the design of such an existing MegaModule.TM. within a certain area on the desired IC chip.
Conventionally, such MegaModules.TM. may be available as standard catalog devices, but usually are designed without testability. An ASIC, employing MegaModules.TM. requires that a custom test program be developed for that particular chip. Because a custom testing program has to be devised for each ASIC, the cost of each test program is essentially duplicated. Thus, there is still a need for generic test programs for modular circuits.
Most of the foregoing prior art test schemes are directed at testing logic functions and do not explicitly have the capability to test analogue or mixed analogue and digital circuits. Much like digital circuits, imbedded mixed signal circuits are often difficult to control or observe during test and characterization. It is also difficult to write generic/reusable test programs for mixed signal circuits. Prior test methods for mixed signal circuits have employed additional pins, modified bond out schemes, and unbonded pads to gain access to and control of analogue modules. Thus, there is still a need for an easy and simple way to test mixed signal circuits.
These and other disadvantages of the prior art are overcome by the present invention, however, and improved methods and apparatus for chip-level testing of analogue or mixed analogue and digital circuitry, as well as system-level testing, are provided.